Clock Generator IP design in 180 nm CMOS Technology
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发表刊物：Analog Integrated Circuits and Signal Processing
摘要：This paper describes a clock generator IP implementation in 180 nm CMOS technology. In this work, a self-biased PLL with proposed direct capacitance multiplication has been implemented, with its pros and cons fully analyzed. The bandwidth tracking capability resulting from the self-biased architecture enables the PLL IP to work over a wide frequency range without degrading the jitter performance. The proposed direct capacitance multiplication also reduces the die area significantly for the implementation of the loop filter capacitor. Power supply noise rejection ability has also been analyzed. Potential start-up issue has been explained, together with the proposed solution. Fabricated in SMIC 180 nm CMOS technology, the total PLL IP occupies only 0.078 mm2 including the integrated loop filter and the decoupling capacitors. The measured output frequency ranges from 50 to 600 MHz with the corresponding duty cycle errors <3 %. The chip consumes 4.7 mA under 1.8 V supply while generating 240 MHz output. The in-band phase noise better than −105 dBc/Hz and phase noise of −100 dBc/Hz at 1 MHz offset are achieved. The reference spur level is about −60 dBc.
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