[4] Z. J. Su, H. X. Cheng, X. Y. Sun, H. D. Sun, and C. J. Zuo, “High-performance floating gate heterostructure with WSe₂-MoS₂ diode channel for neural synapse,” IEEE Electron Device Letters, vol. 44, May 22, 2023. (第一作者，SCI2区，IF 4.5);
Pre One:[3] Z. J. Su, Y. Yan, M. R. Sun, Z. H. Xuan, H. X. Cheng, D. Y. Luo, Z. X. Gao, C. J. Zuo, and H. D. Sun, “Broadband artificial tetrachromatic synaptic devices composed of 2D/3D integrated WSe₂-GaN-based dual-channel floating gate transistors,” Advanced Functional Materials, vol. 34, Apr. 4, 2024. (第一作者，SCI1区 Top，IF 19.4);
Next One:[5] Z. J. Su, Z. H. Xuan, J. Liu, Y. Kang, C.-S. Liu, and C.-J. Zuo, “Sub-femto-Joule energy consumption memory device based on van der Waals heterostructure for in-memory computing,” Chip, vol. 1, Jun. 28, 2022. (第一作者，JCR Q1，IF 7.1);
