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Journal:Journal of Circuits, Systems and Computers

Key Words:Fractional-NFIRinjection-lockedclock generatorin-band noisecascaded PLL

Abstract:This paper proposes a low sub-gigahertz frequency generator with fine frequency resolution. An injection-locked ring oscillator (ILRO) is firstly adopted to obtain multiphase output at integer multiple times crystal oscillator (XO) frequency. Following that, a multiplexer (MUX) selects the output phase according to the output of a delta-sigma modulator (ΔΣM) to achieve high frequency, low in-band noise fractional output. A hybrid type finite impulse response (FIR) filter, which is composed of some MUXs, flip-flops (FFs), digitally-controlled delay units (DCDUs), and a linear multiphase combiner (MPC), is employed in cascading to suppress the quantization noise (Q-noise) at high-frequency offset. An auto-calibration scheme for calibrating the DCDU’s delay has been proposed as well. Simulated in 65nm CMOS, the proposed fractional-N frequency generator exhibits a phase noise performance that is well below −118dBc/Hz from 100kHz to 100MHz offset. The simulation also shows that the power consumption and die area is 10.6mW and 0.3mm2, respectively, with the FIR filter consuming 4.3mW and 0.041mm2.

Translation or Not:no