个人简介
李建华，博士，副研究员，主要从事计算机系统方向的教学和科研工作，主要研究方向为人工智能与数字系统、片上存储和片上网络的交叉研究。近年来在领域内核心会议和期刊上，如IEEE TC，IEEE TPDS，ACM TODAES，电子学报、计算机学报等，发表学术论文40多篇。获2015年香江学者奖，2024年IEEE Andrew P. Sage Best Transaction Paper Award。
研究方向：
>> AI与计算机系统交叉：如基于强化学习的缓存预取策略、基于强化学习的片上网络路由算法设计等；
>> FPGA开发及应用：如基于FPGA 的AI加速器设计、基于FPGA的高并行系统开发（如芯片测试仪器的控制系统开发）。
>> 欢迎： 热爱计算机系统、喜欢折腾底层、想提升动手能力（low-level coding and debugging）的同学联系：jhli @ hfut.edu.cn
>> 喜欢的系统名言：(1) Get your hand dirty! (2) KISS: Keep it simple, stupid! (3) Talk is cheap, show me the code!
教育背景：
>> 2007年获得安庆师范大学计算机科学与技术专业学士学位；
>> 2013年获得中国科学技术大学软件与理论专业博士学位；
>> 2013年8月起，在合肥工业大学计算机与信息学院工作；
>> 2016-2018，香港城市大学，Hong Kong, 香江学者。
讲授课程：
>> 本科生：计算机体系结构、系统硬件综合设计；
学科竞赛方面，指导本科生获得安徽省机器人大赛CPU设计赛道一等奖10余项，获得龙芯杯个人赛二等奖2项。
>> 研究生：高级计算机体系结构、深入理解计算机系统。
论文节选：
[01] Y Ouyang, S Yuan, J Li, H Liang, F-Bypass: A Low-Power Network-on-Chip Design Utilizing Bypass to Improve Network Connectivity. ACM J. Emerg. Technol. Comput. Syst. 20(4): 14:1-14:26 (2024)
[02] W Zhou, Y Ouyang, J Li, D Xu, A transparent virtual channel power gating method for on-chip network routers. Integration. 88: 286-297 (2023)
[03] Y Gu, X Zhang, Y Wang, M Wang, H Yan, Y Ji, Z Liu, J Li, M Dong, WiGRUNT: WiFi-Enabled Gesture Recognition Using Dual-Attention Network. IEEE Trans. Hum. Mach. Syst. 52(4): 736-746 (2022)
[04] Y Ouyang , Q Wang , M Ru , H Liang , J Li, A Novel Low-Latency Regional Fault-Aware Fault-Tolerant Routing Algorithm for Wireless NoC, IEEE Access 8, 2020.
[05] F Shen, Y He, J Zhang, Q Li, J Li , C Xu, Reuse locality aware cache partitioning for last-level cache, Comput. Electr. Eng. 74: 319-330, 2019.
[06] Y Ouyang , Y Zhao, K Xing, Z Huang, H Liang, J Li, Design of Wireless Network on Chip with Priority-Based MAC, Journal of Circuits, Systems, and Computers 28(8): 1950124:1-1950124:18, 2019.
[07] H Wan, F Li, Z Zhou, K Zeng, J Li, CJ Xue, NVLH: Crash-Consistent Linear Hashing for Non-Volatile Memory, NVMSA, 2018.
[08] J Li, M Li, CJ Xue, Y Ouyang, F Shen, Thread criticality assisted replication and migration for chip multiprocessor caches, IEEE Transactions on Computers 66 (10), 1747-1762, 2017.
[09] He, J Zhang, N Jiang, J Li, Feedback learning based dead write termination for energy efficient stt-ram caches, F Shen, Chinese Journal of Electronics 26 (3), 460-467, 2017.
[10] J Li, X An, Y Ouyang, Thread progress aware block migration for dynamic NUCA, 24th Euromicro International Conference on Parallel, Distributed, and Network based Processing, 2016.
[11] Q Li, Y He, J Li, L Shi, Y Chen, CJ Xue, Compiler-assisted refresh minimization for volatile STT-RAM cache, IEEE Transactions on Computers 64 (8), 2169-2181, 2015.
[12] J Li, L Shi, CJ Xue, Y Xu, Dual partitioning multicasting for high-performance on-chip networks, Journal of Parallel and Distributed Computing 74 (1), 1858-1871, 2014.
[13] J Li, L Shi, CJ Xue, Y Xu, Thread progress aware coherence adaption for hybrid cache coherence protocols, IEEE Transactions on Parallel and Distributed Systems 25 (10), 2697-2707, 2014.
[14] J Li, L Shi, Q Li, CJ Xue, Y Chen, Y Xu, W Wang, Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh, ACM Transactions on Design Automation of Electronic Systems (TODAES) 19 (1), 2014.
[15] Q Li, J Li, L Shi, M Zhao, CJ Xue, Y He, Compiler-assisted STT-RAM-based hybrid cache for energy efficient embedded systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (8), 2013.
[16] J Li, L Shi, CJ Xue, Y Chen, Y Xu, Cache coherence enabled adaptive refresh for volatile STT-RAM, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013.
[17] J Li, L Shi, Q Li, CJ Xue, Y Xu, Teaca: Thread progress aware coherence adaption for hybrid coherence protocols, IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 19-26, 2012.
[18] Q Li, L Shi, J Li, CJ Xue, Y He, Code motion for migration minimization in STT-RAM based hybrid cache, IEEE Computer Society Annual Symposium on VLSI, 410-415, 2012.
[19] L Shi, J Li, CJ Xue, X Zhou, Cooperating virtual memory and write buffer management for flash-based storage systems, IEEE transactions on very large scale integration (VLSI) systems 21 (4), 706-719, 2012.
[20] J Li, L Shi, CJ Xue, C Yang, Y Xu, Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache, 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 19-28, 2011.
[21] L Shi, J Li, CJ Xue, C Yang, X Zhou, ExLRU: A unified write buffer cache management for flash memory, Proceedings of the Ninth ACM International Conference on Embedded Systems, 2011.
[22] J Li, CJ Xue, Y Xu, STT-RAM based energy-efficiency hybrid cache for CMPs, IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 31-36, 2011.
[23] J Li, CJ Xue, Y Xu, LADPM: Latency-aware dual-partition multicast routing for mesh-based network-on-chips, IEEE 16th International Conference on Parallel and Distributed Systems, 2010.
中文论文：
[1] 欧阳一鸣,王奇,汤飞扬,周武,李建华.MRNDA：一种基于资源受限片上网络的深度神经网络加速器组播机制研究[J].电子学报,2024,52(03):872-884.
[2] 周义涛,李阳,韩超,赵玉来,汪玲,李建华.适用于S-NUCA异构处理器的任务调度与热管理系统[J].计算机工程,2024,50(02):196-205.
[3] 李悦瑶,胡海洋,王奇,安鑫,李建华.基于动态调整的弹性片上网络路由算法[J].智能计算机与应用,2022,12(10):1-14.
[4] 焦童,陈玲玲,安鑫,李建华.基于重用信息的非易失性缓存动态旁路策略[J].计算机工程,2021,47(04):158-165.
[5] 欧阳一鸣,贾博远,李建华,黄正峰,梁华国.WiNoC中无线通信拥塞与故障感知的容错路由算法[J].电子学报,2020,48(04):662-669.
教育经历
[1] 2008.9-2013.7
中国科学技术大学 | 计算机软件与理论 | 博士学位 | 博士研究生毕业
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